31
0
31
0
31
0
*1 *4
*4
*1 *2
*2
*1 *3
*3
_
_
_
R0 BANK0
R0 BANK0
R0 BANK1
_
_
_
R1 BANK0
R1 BANK0
R1 BANK1
*4
*4
*4
*4
*4
*4
*2
*2
*2
*2
*2
*2
*3
*3
*3
*3
*3
*3
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
_
R2 BANK0
R3 BANK0
R4 BANK0
R5 BANK0
R6 BANK0
R7 BANK0
R2 BANK0
R3 BANK0
R4 BANK0
R5 BANK0
R6 BANK0
R7 BANK0
R2 BANK1
R3 BANK1
R4 BANK1
R5 BANK1
R6 BANK1
R7 BANK1
R8
R8
R8
R9
R9
R9
R10
R11
R12
R13
R14
R15
R10
R11
R12
R13
R14
R15
R10
R11
R12
R13
R14
R15
SR
SR
SR
SSR
SSR
GBR
MACH
MACL
PR
GBR
MACH
MACL
PR
GBR
MACH
MACL
PR
VBR
VBR
PC
PC
PC
SPC
SPC
SGR
DBR
SGR
DBR
*1 *4
*4
*1 *3
*3
_
_
R0 BANK0
R0 BANK1
_
_
R1 BANK0
R1 BANK1
*4
*4
*4
*4
*4
*3
*3
*3
*3
*3
*3
_
_
_
_
_
_
_
_
_
_
_
_
R2 BANK0
R3 BANK0
R4 BANK0
R5 BANK0
R2 BANK1
R3 BANK1
R4 BANK1
R5 BANK1
R6 BANK1
R7 BANK1
R6 BANK0
*4
R7 BANK0
(b) Register configuration in
privileged mode (RB = 1)
(c) Register configuration in
privileged mode (RB = 0)
(a) Register configuration
in user mode
Notes: *1 The R0 register is used as the index register in indexed register-indirect addressing mode and
indexed GBR indirect addressing mode.
*2 Banked registers
*3 Banked registers
Accessed as general registers when the RB bit is set to 1 in the SR register. Accessed only by
LDC/STC instructions when the RB bit is cleared to 0.
*4 Banked registers
Accessed as general registers when the RB bit is cleared to 0 in the SR register. Accessed only by
LDC/STC instructions when the RB bit is set to 1.
Figure 2.2 CPU Register Configuration in Each Processor Mode
Rev. 6.0, 07/02, page 44 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
