22.3.1
Clock and Control Signal Timing
Table 22.25 Clock and Control Signal Timing (HD6417750RBP240)
VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF
Item
Symbol
Min
Max
Unit Figure
EXTAL
PLL1 6-times/PLL2
fEX
16
34
MHz
clock input operation
frequency
PLL1 12-times/PLL2
fEX
14
20
operation
PLL1/PLL2 not operating
fEX
1
34
1000
—
—
4
EXTAL clock input cycle time
tEXcyc
30
3.5
3.5
—
—
25
1
ns
22.1
22.1
22.1
22.1
22.1
EXTAL clock input low-level pulse width tEXL
EXTAL clock input high-level pulse width tEXH
ns
ns
EXTAL clock input rise time
EXTAL clock input fall time
tEXr
tEXf
ns
4
ns
CKIO clock PLL1/PLL2 operating
fOP
120
34
1000
—
—
3
MHz
MHz
ns
output
PLL1/PLL2 not operating
fOP
CKIO clock output cycle time
tcyc
8.3
1
22.2(1)
22.2(1)
22.2(1)
22.2(1)
22.2(1)
22.2(2)
22.2(2)
22.3, 22.5
22.3, 22.5
CKIO clock output low-level pulse width
tCKOL1
ns
CKIO clock output high-level pulse width tCKOH1
1
ns
CKIO clock output rise time
tCKOr
tCKOf
tCKOL2
—
—
3
ns
CKIO clock output fall time
3
ns
CKIO clock output low-level pulse width
—
—
—
—
ns
CKIO clock output high-level pulse width tCKOH2
3
ns
Power-on oscillation settling time
tOSC1
10
10
ms
ms
Power-on oscillation settling time/mode
settling
tOSCMD
SCK2 reset setup time
SCK2 reset hold time
MD reset setup time
MD reset hold time
5(6(7 assert time
tSCK2RS
tSCK2RH
tMDRS
20
20
3
—
—
—
—
—
ns
ns
tcyc
ns
tcyc
22.11
22.3, 22.5, 22.11
22.12
tMDRH
20
20
22.3, 22.5, 22.12
tRESW
22.3, 22.4, 22.5,
22.6, 22.11
PLL synchronization settling time
tPLL
200
3
—
—
—
µs
22.9, 22.10
22.4, 22.6
22.7
Standby return oscillation settling time 1 tOSC2
Standby return oscillation settling time 2 tOSC3
ms
ms
3
Rev. 6.0, 07/02, page 844 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
