22.3
AC Characteristics
In principle, SH7750 Series input should be synchronous. Unless specified otherwise, ensure that
the setup time and hold times for each input signal are observed.
Table 22.17 Clock Timing (HD6417750RBP240)
Item
Symbol
Min
1
Typ
—
Max
240
120
60
Unit
Operating
frequency
CPU, FPU, cache, TLB
External bus
f
MHz
1
—
Peripheral modules
1
—
Table 22.18 Clock Timing (HD6417750RF240)
Item
Symbol
Min
1
Typ
—
Max
240
84
Unit
Operating
frequency
CPU, FPU, cache, TLB
External bus
f
MHz
1
—
Peripheral modules
1
—
60
Table 22.19 Clock Timing (HD6417750BP200M, HD6417750SBP200, HD6417750RBP200)
Item
Symbol
Min
1
Typ
—
Max
200
100
50
Unit
Operating
frequency
CPU, FPU, cache, TLB
External bus
f
MHz
1
—
Peripheral modules
1
—
Table 22.20 Clock Timing (HD6417750RF200)
Item
Symbol
Min
1
Typ
—
Max
200
84
Unit
Operating
frequency
CPU, FPU, cache, TLB
External bus
f
MHz
1
—
Peripheral modules
1
—
50
Table 22.21 Clock Timing (HD6417750SF200)
Item
Symbol
Min
1
Typ
—
Max
200
67
Unit
Operating
frequency
CPU, FPU, cache, TLB
External bus
f
MHz
1
—
Peripheral modules
1
—
50
Rev. 6.0, 07/02, page 842 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
