19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only)
The interrupt mask clear register 00 (INTMSKCLR00) clears the masking of individual interrupt
requests. INTMSKCLR00 is a 32-bit write-only register.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value:
R/W:
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
R/W:
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
—
W
Bit 31 to 0 Interrupt Mask Clear: Each bit selects whether or not to clear the masking of the
interrupt source that corresponds to that bit. For the correspondence between the bits and interrupt
sources, see section 19.3.7, Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00
(SH7750R Only).
Bits 31 to 0
Description
0
Masking of interrupt requests from the source that corresponds to the
bit is not changed
1
Masking of interrupt requests from the source that corresponds to the
bit is cleared
19.3.7 Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00
(SH7750R Only)
The relationship between the bits in these registers and interrupt sources is as shown below.
Table 19.8 Bit Assignments
Bit number
Module
Reserved
TMU
Interrupt
Reserved
TUNI4
31 to 10, 7 to 0
9
8
TMU
TUNI3
Rev. 6.0, 07/02, page 767 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
