15.1.2 Block Diagram
Figure 15.1 shows a block diagram of the SCI.
Internal
data bus
Module data bus
SCBRR1
SCSSR1
SCSCR1
SCSMR1
SCSPTR1
SCRDR1
SCRSR1
SCTDR1
SCTSR1
Pφ
RxD
TxD
SCK
Baud rate
generator
Pφ/4
Transmission/
reception
control
Pφ/16
Pφ/64
Clock
Parity generation
Parity check
External clock
TEI
TXI
RXI
ERI
SCI
SCRSR1: Receive shift register
SCRDR1: Receive data register
SCTSR1: Transmit shift register
SCTDR1: Transmit data register
SCSMR1: Serial mode register
SCSCR1: Serial control register
SCSSR1: Serial status register
SCBRR1: Bit rate register
SCSPTR1: Serial port register
Figure 15.1 Block Diagram of SCI
Rev. 6.0, 07/02, page 595 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
