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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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13.2.14 Refresh Count Register (RFCR)  
The refresh count register (RFCR) is a 10-bit readable/writable counter that counts the number of  
refreshes by being incremented each time the RTCOR register and RTCNT counter values match.  
If the RFCR register value exceeds the count limit specified by the LMTS bit in the RTCSR  
register, the OVF flag is set in the RTCSR register and the RFCR register is cleared.  
RFCR is initialized to H'0000 by a power-on reset, but is not initialized, and retains its contents, in  
a manual reset and in standby mode.  
Bit:  
Bit name:  
Initial value:  
R/W:  
15  
0
14  
0
13  
0
12  
0
11  
0
10  
0
9
8
0
0
R/W  
R/W  
Bit:  
Bit name:  
Initial value:  
R/W:  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
13.2.15 Notes on Accessing Refresh Control Registers  
When the refresh timer control/status register (RTCSR), refresh timer counter (RTCNT), refresh  
time constant register (RTCOR), and refresh count register (RFCR) are written to, a special code  
is added to the data to prevent inadvertent rewriting in the event of program runaway, etc. The  
following procedures should be used for read/write operations.  
Writing to RTCSR, RTCNT, RTCOR, and RFCR: A word transfer instruction must always be  
used when writing to RTCSR, RTCNT, RTCOR, or RFCR. A write cannot be performed with a  
byte transfer instruction.  
When writing to RTCSR, RTCNT, or RTCOR, set B'10100101 in the upper byte and the write  
data in the lower byte, as shown in figure 13.5. When writing to RFCR, set B'101001 in the 6 bits  
starting from the MSB in the upper byte, and the write data in the remaining bits.  
Rev. 6.0, 07/02, page 369 of 986  
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