input clock is the external clock (TCLK) or internal clock (Pφ), TCNT contents are retained in
standby mode.
12.2.6 Timer Control Registers (TCR)
The TCR registers are 16-bit readable/writable registers. There are five TCR registers, one for
each channel.
Each TCR selects the count clock, specifies the edge when an external clock is selected in
channels 0 to 2, and controls interrupt generation when the flag indicating timer counter (TCNT)
underflow is set to 1. TCR2 is also used for channel 2 input capture control, and control of
interrupt generation in the event of input capture.
The TCR registers for channels 0 to 2 are initialized to H'0000 by a power-on or manual reset, but
are not initialized and retain their contents in standby mode. The TCR registers for channels 3 and
4 of the SH7750R are initialized to H'0000 by a power-on reset, but are not initialized and retain
their contents on a manual reset and in standby mode.
1. Channel 0 and 1 TCR bit configuration
Bit:
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
UNF
0
Initial value:
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
—
0
6
—
0
5
UNIE
0
4
3
2
1
0
CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value:
R/W:
0
0
0
0
0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 6.0, 07/02, page 299 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
