12.2.4
Timer Constant Registers (TCOR)
The TCOR registers are 32-bit readable/writable registers. There are TCOR registers, one for each
channel.
When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT,
which continues counting down from the set value.
The TCOR registers for channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual
reset, but are not initialized and retain their contents in standby mode. The TCOR registers for
channels 3 and 4 of the SH7750R are initialized to H'FFFFFFFF by a power-on reset, but are not
initialized and retain their contents on a manual reset and in standby mode.
Bit:
31
30
29
2
1
0
· · · · · · · · · · · · ·
Initial value:
R/W:
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
12.2.5
Timer Counters (TCNT)
The TCNT registers are 32-bit readable/writable registers. There are TCNT registers, one for each
channel.
Each TCNT counts down on the input clock selected by TPSC2–TPSC0 in the timer control
register (TCR).
When a TCNT counter underflows while counting down, the underflow flag (UNF) is set in the
corresponding timer control register (TCR). At the same time, the timer constant register (TCOR)
value is set in TCNT, and the count-down operation continues from the set value.
The TCNT registers for channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual
reset, but are not initialized and retain their contents in standby mode. The TCNT registers for
channels 3 and 4 of the SH7750R are initialized to H'FFFFFFFF by a power-on reset, but are not
initialized and retain their contents on a manual reset and in standby mode.
Bit:
31
30
29
2
1
0
· · · · · · · · · · · · ·
Initial value:
R/W:
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
When the input clock is the on-chip RTC output clock (RTCCLK) in channels 0 to 2, TCNT
counts even in module standby mode (that is, when the clock for the TMU is stopped). When the
Rev. 6.0, 07/02, page 298 of 986
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