MMUCR
31
26 25 24 23
—
18 17 16 15
—
10
9
8
7
3 2 1 0
LRUI
URB
URC
SV
—
TI — AT
SQMD
Entry specification
PTEL
31
29 28
10 9 8 7 6 5 4 3 2 1 0
—
PPN
— V SZ PR SZ C D SHWT
PTEH
31
10
9
8
7
0
VPN
—
ASID
PTEA
31
4
3
2
0
—
TC
SA
Write
Entry 0
Entry 1
Entry 2
ASID [7:0] VPN [31:10]
ASID [7:0] VPN [31:10]
ASID [7:0] VPN [31:10]
V
V
V
PPN [28:10] SZ [1:0] SH C PR [1:0]
PPN [28:10] SZ [1:0] SH C PR [1:0]
PPN [28:10] SZ [1:0] SH C PR [1:0]
D
D
D
WT SA [2:0] TC
WT SA [2:0] TC
WT SA [2:0] TC
Entry 63
ASID [7:0] VPN [31:10]
V
PPN [28:10] SZ [1:0] SH C PR [1:0]
D
WT SA [2:0] TC
UTLB
Figure 3.12 Operation of LDTLB Instruction
Hardware ITLB Miss Handling
3.5.4
In an instruction access, the SH7750 Series searches the ITLB. If it cannot find the necessary
address translation information (i.e. in the event of an ITLB miss), the UTLB is searched by
hardware, and if the necessary address translation information is present, it is recorded in the
ITLB. This procedure is known as hardware ITLB miss handling. If the necessary address
translation information is not found in the UTLB search, an instruction TLB miss exception is
generated and processing passes to software.
Rev. 6.0, 07/02, page 79 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
