Data access to virtual address (VA)
VA is
VA is
in P4 area
VA is
VA is in P0, U0,
or P3 area
in P2 area
in P1 area
On-chip I/O access
0
No
CCR.OCE?
MMUCR.AT = 1
Yes
1
0
CCR.CB?
1
CCR.WT?
1
0
SH = 0
and (MMUCR.SV = 0 or
SR.MD = 0)
No
Yes
VPNs match
and ASIDs match and
V = 1
No
No
VPNs match
and V = 1
Yes
Yes
No
Only one
entry matches
Data TLB miss
exception
Yes
SR.MD?
Data TLB multiple
hit exception
0 (User)
1 (Privileged)
PR?
10
Memory access
00 or 10
11
R/W?
R
01 or 11
R/W?
00 or
01
W
W
W
W
R/W?
R
R/W?
R
R
1
D?
Data TLB protection
violation exception
0
Data TLB protection
violation exception
Initial page write
exception
C = 1
and CCR.OCE = 1
No
Yes
Cache access
in copy-back mode
0
WT?
1
Cache access
in write-through mode
Memory access
(Non-cacheable)
Figure 3.10 Flowchart of Memory Access Using UTLB
Rev. 6.0, 07/02, page 76 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
