INPUT/OUTPUT PINS
5.2 Programmable I/O ports
Figures 5.2.4 and 5.2.5 show the port peripheral circuits.
Direction register
Port latch
P1
P2
P2
P2
P5
P5
P5
2
1
4
6
5
6
7
/R
/TA4IN, P2
(/ TB0IN), P 2
(/ TB2IN), P 2
X
D
0
, P1
6
/R
/TA9IN
(/ TB1IN
(/ INT /RTPTRG0)
X
D
1
3
5
)
Data bus
7
3
/INT
/INT
/INT
5/TB0IN/IDW
6/TB1IN/IDV
7/TB2IN/IDU
Direction register
Port latch
[Inside dotted-line not included]
P1 /T , P1 /T
1
3
X
D0
7
XD1
Output (internal peripheral device)
[Inside dotted-line included]
Data bus
P2
0
/TA4OUT, P2 /TA9OUT
2
Direction register
R
P6
P6
P6
P6
P6
P6
0
1
2
3
4
5
/TA0OUT/W/RTP0
/TA0IN/V/RTP0
/TA1OUT/U/RTP0
/TA1IN/W/RTP0
/TA2OUT/V/RTP1
/TA2IN/U/RTP1
0
P6OUTCUT
Reset
1
1
2
Output (internal peripheral device)
3
Data bus
Port latch
0
1
Direction register
Port latch
P7
0
/AN
0
, P71/AN
1
P72
/AN
2
Data bus
Analog input
Fig. 5.2.4 Port peripheral circuits (1)
7906 Group User’s Manual Rev.2.0
5-5
RENESAS [ RENESAS TECHNOLOGY CORP ]
