4. Register structure
The view of the register structure is described below:
�½2
XXX register (address XX
16
)
Bit
0
Bit name
• • • select bit
�½1
b7 b6 b5 b4 b3 b2 b1 b0
�½5
Function
0:…
1:…
The value is “0” at reading.
b2 b1
X 0
At reset
Undefined
R/W
WO
�½3
1
2
3
4
5
6
7
• • • select bit
00:…
01:…
10:…
11:…
0:…
1:…
0
0
0
0
0
Undefined
0
RW
RW
RO
RW
RW
—
—
• • • flag
Fix this bit to “0.”
This bit is invalid in … mode.
Nothing is assigned.
The value is “0” at reading.
�½6
�½1
Blank
0
1
✕
�½2
0
1
Undefined
�½3
RW
RO
WO
: “0” immediately after reset.
: “1” immediately after reset.
: Undefined immediately after reset.
: Set to “0” or “1” according to the usage.
: Set to “0” at writing.
: Set to “1” at writing.
: Invalid depending on the mode or state. It may be “0” or “1.”
: Nothing is assigned.
�½4
—
: It is possible to read the bit state at reading. The written value becomes valid.
: It is possible to read the bit state at reading. The written value becomes invalid. Accordingly, the written
value may be “0” or “1.”
: The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading.
However, when [“0” at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at
reading. (See
�½5
above.)
: It is impossible to read the bit state. The value is undefined at reading.
However, when [“0” at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at
reading. (See
�½6
above.)
The written value becomes invalid. Accordingly, the written value may be “0” or “1.”
�½4
Invalid for that function or mode.
2
RENESAS [ RENESAS TECHNOLOGY CORP ]
