FLASH MEMORY VERSION
[Precautions for flash memory CPU reprogramming mode]
[Precautions for flash memory CPU reprogramming mode]
1. In the flash memory CPU reprogramming mode, an opcode cannot be fetched for the internal flash memory.
Accordingly, be sure to transfer the reprogramming control software to an area other than the internal flash memory
area, and then execute the software in this area. (See Figure 19.2.2.)
Also, take consideration for instruction description (such as specified addresses, addressing modes) in the repro-
gramming control software since this software is to be executed in an area other than the internal flash memory
area.
2. In order to prevent any interrupt occurrence during the flash memory CPU reprogramming mode, before selecting
this mode, be sure to set the interrupt disable flag (I) to “1” or set the interrupt priority level to “000 ” (interrupts
2
disabled). Also, we recommend to connect pin P6OUTCUT with VCC via a resistor.
Even in the flash memory CPU reprogramming mode, periodically writing to the watchdog timer is required.
Also, an interrupt, hardware reset, or software reset, generated in the CPU reprogramming mode, makes program
runaway. If a program runaway has occurred, be sure to push the microcomputer into the power-on reset state.
3. Commands and data must be read from and written into even-numbered addresses in the user ROM area, 16 bits
at a time.
4. Be sure not to execute the STP instruction in the CPU reprogramming mode.
5. In order to reset the internal flash memory control circuit by using the flash memory reset bit (bit 3 at address 9E16),
be sure to confirm the RY/BY status bit (bit 0 at address 9E16) becomes “1” after writing of “1” to this bit; and then,
write “0” to the flash memory reset bit.
6. Addresses FF9016 to FF9F16 (the user ROM area) are reserved for serial and parallel programmers. Be sure not to
use this area.
7906 Group User’s Manual Rev.2.0
19-18
RENESAS [ RENESAS TECHNOLOGY CORP ]
