SERIAL I/O
11.3 Clock synchronous serial I/O mode
MSB
LSB
Transfer clock output from
or input to CLKi pin (Note).
UARTi receive register
D
0
D
D
1
2
D
D
0
1
D
D
0
5
•
•
•
•
•
•
D
7
D
6
D
4
D
3
D
2
D
1
D0
b7
b0
UARTi receive buffer register
Receive data
Note: This applies when the CLK polarity select bit = “0.”
When the CLK polarity select bit = “1,” data is shifted at the rising edge of
the transfer clock.
Fig. 11.3.11 Receive operation
Receive enable bit
Transmit enable bit
Dummy data is set to UARTi transmit buffer register.
Transmit buffer
empty flag
UARTi transmit register←UARTi transmit buffer
RTS
i
1/fEXT
CLK
i
Receive data is taken in.
D0
D1
D2
D3
D4
D5
D7
D0
D1
D2
D3
D4
D5
D6
RxD
i
UARTi receive register→UARTi receive buffer register
UARTi receive buffer register is read o
Receive complete flag
UARTi receive
interrupt request bit
Cleared to “0” when interrupt request is accepted or
cleared to “0” by software.
When the CLKi pin’s input level is “H,” be sure to sati
the following conditions:
ꢀꢀWriting of dummy data to UARTi transmit buffer re
ꢀꢀTransmit enable bit = “1”
The above timing diagram applies when the following
conditions are satisfied:
ꢀꢀExternal clock selected
ꢀꢀRTS function selected
ꢀꢀCLK polarity select bit = “0”
ꢀꢀReceive enable bit = “1”
f
EXT: Frequency of external clock
Fig. 11.3.12 Example of receive timing (when external clock selected)
7906 Group User’s Manual Rev.2.0
11-33
RENESAS [ RENESAS TECHNOLOGY CORP ]
