SERIAL I/O
11.3 Clock synchronous serial I/O mode
UART0 transmit/receive mode register (Address 3016
UART1 transmit/receive mode register (Address 3816
)
)
b7
b0
When extenal clock is selected
When internal clock is selected
ꢀ
ꢀ
ꢀ
0
0
0
1
Selection of clock synchronous serial
I/O mode
UART0 baud rate register (BRG0) (Address 3116
UART1 baud rate register (BRG1) (Address 3916
)
)
Internal/External clock select bit
0: Internal clock
b7
b0
1: External clock
ꢀ: It may be either “0” or “1.”
Can be set to “0016” to “FF16.”
UART0 transmit/receive control register 0 (Address 3416
UART1 transmit/receive control register 0 (Address 3C16
b7 b0
)
)
Port P1 direction register (Address 516
b7 b0
)
BRG count source select bits
b1 b0
0
0 0 : f
2
0 1 : f16
1 0 : f64
1 1 : f512
Pin RxD
Pin RxD
0
1
CTS/RTS function select bit
0: CTS function selected
1: RTS function selected
UART0 receive interrupt control register (Address 7216
UART1 receive interrupt control register (Address 7416
)
)
CTS/RTS enable bit
0: CTS/RTS function is enabled.
1: CTS/RTS function is disabled.
b7
b0
UARTi receive interrupt mode select bit
0: Reception interrupt
1: Reception error interrupt
Interrupt priority level select bits
When using interrupts, set these bits to
one of levels 1 to 7.
When disabling interrupts, set these bits
to level 0.
CLK polarity select bit
0: At the rising edge of the transfer
clock, receive data is input.
1: At the falling edge of the transfer
clock, receive data is input.
Transfer format select bit
0: LSB first
1: MSB first
UART0 transmit buffer register (Address 3216
UART1 transmit buffer register (Address 3A16
b7 b0
)
)
Serial I/O pin control register (Address AC16
b7 b0
)
Dummy data is set.
CTS
0: CTS
CTS /RTS
0: CTS /RTS
TxD /P1 switch bit (Note 2)
0: Functions as TxD
1: Functions as P1
TxD /P1 switch bit (Note 2)
0: Functions as TxD
1: Functions as P1
0
/RTS
0
separate select bit
0 are used together (Note 1).
0
/RTS
separate select bit
are used together (Note 1).
1
1
UART0 transmit/receive control register 1 (Address 3516
UART1 transmit/receive control register 1 (Address 3D16
)
)
1
1
0
3
0
.
b7
b0
3
.
1
1
1
7
1
.
7
.
Transmit enable bit
1: Transmission enabled
Notes 1: In the clock synchronous serial I/O
mode, CTS/RTS separation cannot
Reception enable bit
1: Reception enabled
i
i
be selected. (Refer to section “[Pre-
cautions for clock synchronous
serial I/O mode].”)
2: When only reception is performed, if
these bits = “1,” the TxDi pin can be
Note: Set the receive enable bit
and the transmit enable
bit to “1” simultaneously.
used as a programmable I/O port
pin.
Reception starts.
Fig. 11.3.8 Initial setting example for relevant registers when receiving
7906 Group User’s Manual Rev.2.0
11-29
RENESAS [ RENESAS TECHNOLOGY CORP ]
