SERIAL I/O
11.3 Clock synchronous serial I/O mode
11.3.5 Method of reception
Figure 11.3.8 shows an initial setting example for relevant registers when receiving. Reception is started
when all of the following conditions (ꢀ to ꢀ) have been satisfied. When an external clock is selected,
satisfy conditions ꢀ to ꢀ with the following preconditions satisfied.
<Preconditions>
The CLK
The CLK
i
pin’s input is at “H” level (External clock selected, when the CLK polarity select bit = “0” ).
pin’s input is at “L” level (External clock selected, when the CLK polarity select bit = “1”).
i
Note: When an internal clock is selected, the above preconditions are ignored.
ꢀ Dummy data is present in the UARTi transmit buffer register (transmit buffer empty flag = “0”)
ꢀ Reception is enabled (receive enable bit = “1”).
ꢀ Transmission is enabled (transmit enable bit = “1”).
By connecting the RTS
i
pin (receiver side) and CTS pin (transmitter side), the timing of transmission and
i
that of reception can be matched. For details, refer to section “11.3.6 Receive operation.”
When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer
to “CHAPTER 6. INTERRUPTS.”
Figure 11.3.9 shows processing after reception is completed.
7906 Group User’s Manual Rev.2.0
11-28
RENESAS [ RENESAS TECHNOLOGY CORP ]
