DESCRIPTION
1.4 Block diagram
1.4 Block diagram
Figure 1.4.1 shows the M37906 block diagram.
Data Bus (Even)
Data Bus (Odd)
Data Buffer DQ
0
(8)
(8)
Data Buffer DQ
1
Data Buffer DQ
2
(8)
(8)
Data Buffer DQ
3
Address Bus
Instruction Queue Buffer Q
0
(8)
(8)
(8)
(8)
Instruction Queue Buffer Q
1
Instruction Queue Buffer Q
Instruction Queue Buffer Q
Instruction Queue Buffer Q
Instruction Queue Buffer Q
Instruction Queue Buffer Q
2
3
4
5
6
(8)
(8)
(8)
(8)
Instruction Queue Buffer Q
7
Instruction Queue Buffer Q
8
(8)
(8)
Instruction Queue Buffer Q
9
Incrementer (24)
Program Address Register PA (24)
Data Address Register DA (24)
Incrementer/Decrementer (24)
Program Counter PC (16)
Program Bank Register PG (8)
Data bank Register DT (8)
Input Buffer Register IB (16)
Processor Status Register PS (11)
Direct Page Register DPR0 (16)
Direct Page Register DPR1 (16)
Direct Page Register DPR2 (16)
Direct Page Register DPR3 (16)
Stack Pointer S (16)
Index Register Y (16)
Index Register X (16)
Accumulator B (16)
Accumulator A (16)
Arithmetic Logic
Unit (16)
Fig. 1.4.1 M37906 block diagram
7906 Group User’s Manual Rev.2.0
1-6
RENESAS [ RENESAS TECHNOLOGY CORP ]
