TIMER A
7.4 Event counter mode
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A4 register (Addresses 4F16, 4E16)
Timer A9 register (Addresses CF16, CE16)
(b15)
b7
(b8)
b0 b7
b0
Function
Any value in the range from “000016” to “FFFF16” can be set.
Bit
At reset R/W
RW
15 to 0
Undefined
Assuming that the set value = n, the counter divides the count source frequency by (n + 1)
during countdown, or by (FFFF16 – n + 1) during countup.
When reading, the register indicates the counter value.
Note: Reading from or writing to this register must be performed in a unit of 16 bits.
b7 b6 b5 b4 b3 b2 b1 b0
Timer Aj mode register (j = 0 to 2, 4, 9) (Addresses 5616 to 5816, 5A16, DA16)
X X 0
0 1
Bit
0
Bit name
Function
0 1 : Event counter mode
At reset R/W
b1 b0
Operating mode select bits
0
0
0
RW
RW
RW
1
2
0 : No pulse output (TAjOUT pin functions as a
programmable I/O port pin.)
Pulse output function select bit
1 : Pulse output (TAjOUT pin functions as a pulse
output pin.)
Count polarity select bit
3
4
0 : Counts at falling edge of external signal
1 : Counts at rising edge of external signal
0
0
RW
RW
Up-down switching factor select
bit
0 : Contents of up-down register
1 : Input signal to TAjOUT pin
Fix this bit to “0” in event counter mode.
5
6
7
0
0
0
RW
RW
RW
These bits are invalid in event counter mode.
X : It may be either “0” or “1.”
Fig. 7.4.1 Structures of timer Aj register and timer Aj mode register in event counter mode
7906 Group User’s Manual Rev.2.0
7-20
RENESAS [ RENESAS TECHNOLOGY CORP ]
