TIMER A
7.4 Event counter mode
7.4.2 Operation in event counter mode
ꢀ When the count start bit is set to “1,” the counter starts counting of the count source’s valid edge.
ꢀ When a counter underflow or overflow occurs, the reload register’s contents are reloaded, and counting
continues.
ꢀ The timer Aj interrupt request bit is set to “1” at the underflow or overflow in ꢀ.
The interrupt request bit remains set to “1” until the interrupt request is accepted or until the interrupt
request bit is cleared to “0” by software.
Figure 7.4.4 shows an example of operation in the event counter mode.
FFFF16
Starts counting.
n
000016
Time
Set to “1” by software.
Count start bit
Set to “1” by software.
Up-down bit
Timer Aj interrupt
request bit
Cleared to “0” when interrupt request is accepted or cleared by software.
n : Reload register’s contents
Note: The above applies when the up-down bit’s contents are selected as the up-down switching factor (i.e., up-down
switching factor select bit = “0” ).
Fig. 7.4.4 Example of operation in event counter mode (without pulse output and two-phase pulse
signal processing functions)
7906 Group User’s Manual Rev.2.0
7-23
RENESAS [ RENESAS TECHNOLOGY CORP ]
