TIMER A
7.4 Event counter mode
7.4 Event counter mode
Timer Aj (j = 0 to 2, 4, 9) is equipped with the event counter mode. In this mode, the timer counts an external
signal.
Tables 7.4.1 and 7.4.2 list the specifications of the event counter mode. Figure 7.4.1 shows the structures
of the timer Aj register and timer Aj mode register in the event counter mode.
Each of timers A3, A5 to A8 is not equipped with this mode.
Table 7.4.1 Specifications of event counter mode (when not using two-phase pulse signal processing
function)
Item
Specifications
ꢀ External signal input to the TAjIN pin
Count source
ꢀ The count source’s valid edge can be selected from the falling edge
and the rising edge by software.
Count operation
Division ratio
ꢀ Countup or countdown can be switched by external signal or software.
ꢀ When a counter overflow or underflow occurs, reload register’s con-
tents are reloaded, and counting continues.
ꢀ For countdown
1
(n + 1)
n: Timer Aj register’s set value
ꢀ For countup
1
(FFFF16 – n + 1)
Count start condition
Count stop condition
Interrupt request occurrence timing
TAjIN pin’s function
When the count start bit is set to “1.”
When the count start bit is cleared to “0.”
When a counter overflow or underflow occurs.
Count source input
TAjOUT pin’s function
Programmable I/O port pin, pulse output pin, or countup/countdown
switch signal input pin
Read from timer Aj register
Write to timer Aj register
Counter value can be read out.
ꢀ While counting is stopped
When a value is written to timer Aj register, it is written to both of
the reload register and counter.
ꢀ While counting is in progress
When a value is written to timer Aj register, it is written only to the
reload register. (Transferred to the counter at the next reload timing.)
7906 Group User’s Manual Rev.2.0
7-18
RENESAS [ RENESAS TECHNOLOGY CORP ]
