TIMER A
7.3 Timer mode
7.3.2 Operation in timer mode
➀ When the count start bit is set to “1,” the counter starts counting of the count source.
➀ When a counter underflow occurs, the reload register’s contents are reloaded, and counting continues.
➀ The timer Ai interrupt request bit is set to “1” at the underflow in ➀. The interrupt request bit remains
set to “1” until the interrupt request is accepted or until the interrupt request bit is cleared to “0” by
software.
Figure 7.3.3 shows an example of operation in the timer mode.
FFFF16
n
Starts counting.
Stops counting.
(1 / f
i
) ➀ (n+1)
Restarts counting.
000016
Time
Set to “1” by software.
Set to “1” by software.
Cleared to “0” by software.
Count start bit
Timer Ai interrupt
request bit
Cleared to “0” when interrupt request is
accepted or cleared by software.
fi
: Frequency of count source
n : Reload register’s contents
Fig. 7.3.3 Example of operation in timer mode (without pulse output and gate functions)
7906 Group User’s Manual Rev.2.0
7-14
RENESAS [ RENESAS TECHNOLOGY CORP ]
