TIMER A
7.2 Block description
7.2.6 Port P2 and port P6 direction registers
The I/O pins of timers A0 to A2 are multiplexed with port P6 pins, and the I/O pins of timers A4 and A9
are multiplexed with port P2 pins. When using these pins as timer Aj (j = 0 to 2, 4, 9)’s input pins, clear
the corresponding bits of the port P6 and port P2 direction registers to “0” in order to set these port pins
for the input mode. When used as timer Aj’s output pins, these pins are forcibly set to the output pins of
timer Aj regardless of the direction registers’ contents. Figure 7.2.7 shows the relationship between the port
P6 and port P2 direction registers and the timer Aj’s I/O pins.
Note that each bit of the port P6 direction register becomes “0” by an input of a falling edge to pin
P6OUTCUT. (Refer to section “5.2.3 Pin P6OUTCUT/INT .”) When switching the output pins of timers A0 to
4
A2 to the port output pins, the following procedure is required.
➀ Return the input level at pin P6OUTCUT to “H.”
➀ Write data to the port P6 register’s bit corresponding to the port P6 pin, where data is to be output.
➀ Set “1” to the port P6 direction register’s bit corresponding to the above P6 register’s bit; therefore, this
bit enters the output mode.
When the input level at pin P6OUTCUT = “L,” no bit of the port P6 direction register can be set to “1.”
b7 b6 b5 b4 b3 b2 b1 b0
Port P6 direction register (Address 1016
)
Bit
0
Corresponding pin
Pin TA0OUT (Pin W/RTP00)
Pin TA0IN (Pin V/RTP01)
Pin TA1OUT (Pin U/RTP02)
Pin TA1IN (Pin W/RTP03)
Pin TA2OUT (Pin V/RTP10)
Pin TA2IN (Pin U/RTP11)
Nothing is assigned.
Functions
At reset R/W
0
RW
RW
RW
RW
RW
RW
—
0 : Input mode
1 : Output mode
1
0
2
0
When using this pin as timer Aj’s input pin, be sure
to clear the corresponding bit to “0.”
3
0
4
0
0
5
7, 6
Undefined
Notes 1: Each of bits 0 to 5 becomes “0” by an input of the falling edge to pin P6OUTCUT/INT
INT .”)
2: The pins in ( ) are I/O pins of other internal peripheral devices, which are multiplexed.
4. (Refer to section “5.2.3 Pin P6OUTCUT/
4
b7 b6 b5 b4 b3 b2 b1 b0
Port P2 direction register (Address 816
)
Bit
0
Corresponding pin
Functions
At reset R/W
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Pin TA4OUT
0 : Input mode
1
1 : Output mode
Pin TA4IN
Pin TA9OUT
Pin TA9IN
Pin TB0IN
Pin TB1IN
Pin TB2IN
2
When using this pin as timer Aj’s input pin, be sure
to clear the corresponding bit to “0.”
3
4
(Note 1)
(Note 2)
(Note 3)
5
6
7
Pin INT3/RTPTRG0 (Note 4)
Notes 1: This applies when the TB0IN pin select bit (bit 0 at address AE16) = 1.
2: This applies when the TB1IN pin select bit (bit 1 at address AE16) = 1.
3: This applies when the TB2IN pin select bit (bit 2 at address AE16) = 1.
4: This applies when the INT3/RTPTRG0 pin select bit (bit 3 at address AE16) = 1.
5: The pins in ( ) are I/O pins of other internal peripheral devices, which are multiplexed.
Fig. 7.2.7 Relationship between port P6 and port P2 direction registers and timer Aj’s I/O pins
7906 Group User’s Manual Rev.2.0
7-10
RENESAS [ RENESAS TECHNOLOGY CORP ]
