TIMER A
7.2 Block description
7.2.2 Timer A clock division select register
In the timer mode, one-shot pulse mode, and pulse width modulation (PWM) mode, the count source select
bits (bits 6 and 7 at addresses 56
16
to 5A
16
, D6
16
to DA
16
), and timer A clock division select bits (bits 0 and
1 at address 45
16
) select the count source. Figure 7.2.3 shows the structure of the timer A clock division
select register. Table 7.2.3 lists the count source (in the timer mode, one-shot pulse mode, and pulse width
modulation (PWM) mode).
Each of timers A3 and A5 to A8 is equipped with the timer mode only.
Timer A clock division select register (Address 45
16
)
Bit
0
1
7 to 2
The value is “0” at reading.
Bit name
Timer A clock division select bits See Table 7.2.3.
Function
b7 b6 b5 b4 b3 b2 b1 b0
At reset
0
0
0
R/W
RW
RW
–
Fig. 7.2.3 Structure of timer A clock division select register
Table 7.2.3 Count source (in timer mode, one-shot
pulse mode, and pulse width modulation
(PWM) mode)
Count source select bits
(bits 6 and 7 at addresses
56
16
to 5A
16
, D6
16
to DA
16
)
00
01
10
11
Timer A clock division select bits
(bits 0 and 1 at address 45
16
)
01
10
11
00
f
1
f
1
f
2
f
16
f
16
f
64
Do not
f
64
f
64
f
512
select.
f
512
f
4096
f
4096
7-6
7906 Group User’s Manual Rev.2.0
RENESAS [ RENESAS TECHNOLOGY CORP ]
