TIMER A
7.2 Block description
7.2 Block description
Figure 7.2.1 shows the block diagram of timer Aj (j = 0 to 2, 4, 9). Figure 7.2.2 shows the block diagram
of timer Ak (k = 3, 5 to 8). Explanation of registers relevant to timer A is described below.
Timer A clock division
select bits (Note)
Count source
select bit
f
2
f
1
Data bus (odd)
Data bus (even)
f
f
16
64
f
512
(Low-order 8 bits)
(High-order 8 bits)
f
4096
Timer mode
One-shot pulse mode
PWM mode
Timer Aj reload register (16)
Timer Aj counter (16)
Timer Aj
interrupt
request bit
Timer mode
(Gate function)
Event counter mode
Trigger
Polarity
switching
TAjIN
Count start bit
Countup/Countdown
switching
(Always “countdown” except
for in the event counter
mode)
Countdown
Up-down bit
Pulse output
function select bit
Toggle
F.F.
TAjOUT
Note: Common to timers A0 to A9.
Fig. 7.2.1 Block diagram of timer Aj (j = 0 to 2, 4, 9)
Data bus (odd)
Data bus (even)
Timer A clock division
select bits (Note)
Count source
select bit
(High-order 8 bits)
(Low-order 8 bits)
f
f
2
1
Timer Ak reload register (16)
Timer Ak counter (16)
f
f
16
64
f
512
Timer mode
Timer Ak
interrupt
request bit
f
4096
Count start bit
Note: Common to timers A0 to A9.
Fig. 7.2.2 Block diagram of timer Ak (k = 3, 5 to 8)
7906 Group User’s Manual Rev.2.0
7-4
RENESAS [ RENESAS TECHNOLOGY CORP ]
