HM-6504
Timing Waveforms (Continued)
(7)
(8)
(7)
TAVEL TELAX
TAVEL
NEXT ADD
A
ADD VALID
(18) TELEL
(5) TELEH
(6)
TEHEL
(6) TEHEL
E
(11)
TWLEL
(11)
(13)
TWLEL TELWH
W
(15)
(17)
(15)
TDVEL TELDX
TDVEL
D
0
DATA VALID
NEXT DATA
HIGH-Z
HIGH-Z
TIME
REFERENCE
-1
0
1
2
3
4
FIGURE 12. EARLY WRITE CYCLE
TRUTH TABLE
INPUTS
OUTPUT
TIME REFERENCE
E
W
X
L
A
X
V
X
X
X
V
D
X
V
X
X
X
V
Q
Z
Z
Z
Z
Z
Z
FUNCTION
-1
0
1
2
3
4
H
Memory Disabled
Cycle Begins, Addresses are Latched
Write in Progress Internally
L
X
X
X
L
Write Completed
H
Prepare for Next Cycle (Same as - 1)
Cycle Ends, Next Cycle Begins (Same as 0)
The early write cycle is the only cycle where the output is
guaranteed not to become active. On the falling edge of E
(T = 0), the addresses, the write signal, and the data input
are latched in on-chip registers. The logic value of W at the
time E falls, determines the state of the output buffer for that
cycle. Since W is low when E falls, the output buffer is
latched into the high impedance state and will remain in that
131
RENESAS [ RENESAS TECHNOLOGY CORP ]
