HM-6504
Functional Diagram
LSB
A
A
A8
A7
A6
A0
A1
A2
6
6
LATCHED
ADDRESS
REGISTER
GATED
64 x 64
ROW
MATRIX
64
DECODER
L
G
64
G
Q
GATED COLUMN
DECODER AND
DATA I/O
D
Q
D
Q
D
LATCH
L
LATCH
L
A
A
D
Q
Q
W
LATCH
L
6
6
A
A
LATCHED
ADDRESS
REGISTER
E
L
L
D
LATCH
LSB A11 A5 A4 A3 A9 A10
NOTES:
13. All lines active high-positive logic.
14. Three-state Buffers: A high → output active.
15. Control and Data Latches: L low → Q = D and Q latches on rising edge of L.
16. Address Latches: Latch on falling edge of E.
17. Gated Decoders: Gate on rising edge of G.
127