RTL8201E(L)
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM..........................................................................................................................................................3
FIGURE 2. RTL8201EL LQFP-48 PIN ASSIGNMENTS....................................................................................................................4
FIGURE 3. RTL8201E QFN-32 PIN ASSIGNMENT..........................................................................................................................5
FIGURE 4. READ CYCLE...............................................................................................................................................................19
FIGURE 5. WRITE CYCLE .............................................................................................................................................................19
FIGURE 6. LED AND PHY ADDRESS CONFIGURATION ................................................................................................................21
FIGURE 7. POWER ON SEQUENCE ................................................................................................................................................26
FIGURE 8. PHY RESET SEQUENCE...............................................................................................................................................27
FIGURE 9. MII TRANSMISSION CYCLE TIMING-1.........................................................................................................................29
FIGURE 10. MII TRANSMISSION CYCLE TIMING-2.........................................................................................................................29
FIGURE 11. MII RECEPTION CYCLE TIMING-1 ..............................................................................................................................30
FIGURE 12. MII RECEPTION CYCLE TIMING-2 ..............................................................................................................................30
FIGURE 13. RMII TRANSMISSION CYCLE TIMING .........................................................................................................................31
FIGURE 14. RMII RECEPTION CYCLE TIMING ...............................................................................................................................31
FIGURE 15. SNI TRANSMISSION CYCLE TIMING-1 ........................................................................................................................32
FIGURE 16. SNI TRANSMISSION CYCLE TIMING-2 ........................................................................................................................32
FIGURE 17. SNI RECEPTION CYCLE TIMING-1 ..............................................................................................................................33
FIGURE 18. SNI RECEPTION CYCLE TIMING-2 ..............................................................................................................................33
FIGURE 19. MDC/MDIO TIMING..................................................................................................................................................34
FIGURE 20. MAC TO PHY TRANSMISSION WITHOUT COLLISION .................................................................................................34
FIGURE 21. PHY TO MAC RECEPTION WITHOUT ERROR .............................................................................................................35
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
vi
Track ID: JATR-1076-21 Rev. 1.3
REALTEK [ Realtek Semiconductor Corp. ]
