RTL8201CL
Datasheet
TXCLK
TXEN
TXD[0:3]
t
t
7
9
6
CRS
t
t
8
TPTX+-
Figure 7. MII Transmission Cycle Timing-2
8.2.2. MII Reception Cycle Timing
Table 34. MII Reception Cycle Timing
Symbol
Description
RXCLK high pulse width
Minimum
Typical
20
Maximum
Unit
ns
t1
100Mbps
10Mbps
14
140
14
26
260
26
200
ns
t2
t3
t4
t5
t6
t7
t8
t9
RXCLK low pulse width
RXCLK period
100Mbps
20
ns
10Mbps
100Mbps
140
200
40
260
ns
ns
10Mbps
100Mbps
10Mbps
100Mbps
400
ns
ns
ns
ns
RXER, RXDV, RXD[0:3] setup
to RXCLK rising edge
10
6
RXER, RXDV, RXD[0:3] hold
after RXCLK rising edge
10
10Mbps
100Mbps
6
ns
ns
Receive frame to CRS high
130
10Mbps
100Mbps
2000
240
ns
ns
End of receive frame to CRS low
10Mbps
1000
150
ns
ns
Receive frame to sampled edge of 100Mbps
RXDV
10Mbps
100Mbps
3200
120
ns
ns
End of receive frame to sampled
edge of RXDV
10Mbps
1000
ns
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
25
Track ID: JATR-1076-21 Rev. 1.24
REALTEK [ Realtek Semiconductor Corp. ]
