RTL8201CL
Datasheet
Symbol
Condition
Minimum
Vdd -1.16V
Vdd -1.81V
Vdd -1.02V
Maximum
Vdd -0.88V
Vdd -1.47V
PECL VIH
PECL VIL
PECL VOH
PECL VOL
PECL Input High Vol.
PECL Input Low Vol.
PECL Output High Vol.
PECL Output Low Vol.
Vdd -1.62V
8.2. AC Characteristics
8.2.1. MII Transmission Cycle Timing
Table 33. MII Transmission Cycle Timing
Symbol
Description
Minimum
Typical
Maximum
Unit
t1
TXCLK high pulse width
100Mbps
10Mbps
14
20
26
ns
140
200
260
ns
t2
TXCLK low pulse width
TXCLK period
100Mbps
10Mbps
14
20
26
ns
ns
140
200
260
t3
t4
100Mbps
10Mbps
100Mbps
40
400
24
ns
ns
ns
TXEN, TXD[0:3] setup to
TXCLK rising edge
10
5
10Mbps
100Mbps
ns
ns
t5
t6
t7
TXEN, TXD[0:3] hold after
TXCLK rising edge
10
25
10Mbps
100Mbps
5
ns
ns
TXEN sampled to CRS high
40
10Mbps
400
160
ns
ns
TXEN sampled to CRS low
100Mbps
10Mbps
2000
140
ns
ns
t8
t9
Transmit latency
100Mbps
60
70
10Mbps
100Mbps
10Mbps
2000
170
ns
ns
ns
Sampled TXEN inactive to end
of frame
100
Figure 6 shows an example of a packet transfer from MAC to PHY on the MII interface.
t
3
VIH(min)
VIL(max)
TXCLK
t
t
2
1
t
t
5
4
VIH(min)
VIL(max)
TXD[0:3]
TXEN
Figure 6. MII Transmission Cycle Timing-1
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
24
Track ID: JATR-1076-21 Rev. 1.24
REALTEK [ Realtek Semiconductor Corp. ]
