RTL8110SC(L)
Datasheet
6.2.2. Target Write
A Target Write operation starts with the system generating FRAMEB, Address, and Command (0011b or
0111b). If the upper 24 bits on the address bus match IOAR (for I/O reads) or MEM (for memory reads),
the RTL8110SC(L) will generate DEVSELB 2 clock cycles later. On the 2nd cycle after the assertion of
DEVSELB, the device will monitor the IRDYB signal. If IRDYB is asserted at that time, the
RTL8110SC(L) will assert TRDYB. On the next clock the 32-bit double word will be latched in, and
TRDYB will be forced HIGH for 1 cycle and then tri-stated. Target write operations must be 32-bits
wide.
If FRAMEB is asserted beyond the assertion of IRDYB, the RTL8110SC(L) will still latch the first
double word as described above, but will also issue a Disconnect. That is, it will assert the STOPB signal
with TRDYB. STOPB will remain asserted until FRAMEB is detected as deasserted.
Figure 5. Target Write Operation
Integrated Gigabit Ethernet Controller (LOM) (MiniPCI) 11
Track ID: JATR-1076-21 Rev. 1.2
REALTEK [ Realtek Semiconductor Corp. ]
