RTL8110SC(L)
Datasheet
6.2.3. Master Read
A Master Read operation starts with the RTL8110SC(L) asserting REQB. If GNTB is asserted within
2 clock cycles, FRAMEB, Address, and Command will be generated 2 clocks after REQB (Address and
FRAMEB for 1 cycle only). If GNTB is asserted 3 cycles or later, FRAMEB, Address, and Command
will be generated on the clock following GNTB.
The device will wait for 8 cycles for the assertion of DEVSELB. If DEVSELB is not asserted within
8 clocks, the device will issue a master abort by asserting FRAMEB HIGH for 1 cycle, and IRDYB will
be forced HIGH on the following cycle. Both signals will become tri-state on the cycle following their
deassertion.
On the clock edge after the generation of Address and Command, the address bus will become tri-state,
and the C/BE bus will contain valid byte enables. On the clock edge after FRAMEB was asserted,
IRDYB will be asserted (and FRAMEB will be deasserted if this is to be a single read operation). On the
clock where both TRDYB and DEVSELB are detected as asserted, data will be latched in (and the byte
enables will change if necessary). This will continue until the cycle following the deassertion of
FRAMEB.
On the clock where the second to last read cycle occurs, FRAMEB will be forced HIGH (it will be
tri-stated 1 cycle later). On the next clock edge that the device detects TRDYB asserted, it will force
IRDYB HIGH. It too will be tri-stated 1 cycle later. This will conclude the read operation. The
RTL8110SC(L) will never force a wait state during a read operation.
Figure 6. Master Read Operation
Integrated Gigabit Ethernet Controller (LOM) (MiniPCI) 12
Track ID: JATR-1076-21 Rev. 1.2
REALTEK [ Realtek Semiconductor Corp. ]
