RTL8110SC(L)
Datasheet
Symbol
Type
Pin No
Description
REQB
T/S
30
Request: The RTL8110SC(L) will assert this signal low to request the
ownership of the bus from the central arbiter.
IDSEL
INTAB
I
46
25
Initialization Device Select: This pin allows the device to identify when
configuration read/write transactions are intended for it.
Interrupt A: Used to request an interrupt. It is asserted low when an
interrupt condition occurs, as defined by the Interrupt Status, Interrupt
Mask.
O/D
IRDYB
S/T/S
S/T/S
63
Initiator Ready: This indicates the initiating agent’s ability to complete the
current data phase of the transaction.
As a bus master, this signal will be asserted low when the device is ready to
complete the current data phase transaction. This signal is used in
conjunction with the TRDYB signal. Data transaction takes place at the
rising edge of CLK when both IRDYB and TRDYB are asserted low. As a
target, this signal indicates that the master has put data on the bus.
TRDYB
67
Target Ready: This indicates the target agent’s ability to complete the
current phase of the transaction.
As a bus master, this signal indicates that the target is ready for the data
during write operations, or is ready to provide the data during read
operations.
As a target, this signal will be asserted low when the (slave) device is ready
to complete the current data phase transaction. This signal is used in
conjunction with the IRDYB signal. Data transaction takes place at the
rising edge of CLK, when both IRDYB and TRDYB are asserted low.
PAR
T/S
76
Parity: This signal indicates even parity across PCIADPIN31-0 and
CBEB3-0 including the PAR pin. PAR is stable and valid one clock after
each address phase. For data phase, PAR is stable and valid one clock after
either IRDYB is asserted on a write transaction or TRDYB is asserted on a
read transaction. Once PAR is valid, it remains valid until one clock after
the completion of the current data phase. As a bus master, PAR is asserted
during address and write data phases. As a target, PAR is asserted during
read data phases.
M66EN
PERRB
SERRB
I
88
70
75
66MHZ_ENABLE: This pin indicates to the device whether the bus
segment is operating at 66 or 33MHz. When this pin (active high) is
asserted, the current PCI bus segment that the device resides on operates in
66MHz mode. If this pin is de-asserted, the current PCI bus segment
operates in 33MHz mode.
Parity Error: This pin is used to report data parity errors during all PCI
transactions except a Special Cycle. PERRB is driven active (low) two
clocks after a data parity error is detected by the device receiving data, and
the minimum duration of PERRB is one clock for each data phase with
parity error detected.
S/T/S
O/D
System Error: If an address parity error is detected and Configuration Space
Status register bit 15 (detect parity error) is enabled, the device asserts the
SERRB pin low and bit 14 of the Status register in Configuration Space.
STOPB
S/T/S
I
69
27
Stop: Indicates that the current target is requesting the master to stop the
current transaction.
Reset: When PCIRSTB is asserted low, the device performs an internal
system hardware reset. PCIRSTB must be held for a minimum period
of 120ns.
PCIRSTB
Integrated Gigabit Ethernet Controller (LOM) (MiniPCI)
6
Track ID: JATR-1076-21 Rev. 1.2
REALTEK [ Realtek Semiconductor Corp. ]
