RTL8110SC(L)
Datasheet
5.2. PCI Interface
Table 2. PCI Interface
Symbol
Type
Pin No
Description
PCIADPIN31-0
T/S
33, 34, 36, AD31-0: Low 32-bit PCI address and data multiplexed pins. The address
37, 39, 40, phase is the first clock cycle in which FRAMEB is asserted. During the
42, 43, 47, address phase, AD31-0 contains a physical address (32 bits). For I/O, this is
49, 50, 53, a byte address, and for configuration and memory, it is a double-word
55, 57, 58, address. The RTL8110SC(L) supports both big-endian and little-endian byte
59, 79, 82, ordering. Write data is stable and valid when IRDYB is asserted. Read data
83, 85, 86, is stable and valid when TRDYB is asserted. Data I is transferred during
87, 89, 90, those clocks where both IRDYB and TRDYB are asserted.
93, 95, 96,
97, 98, 102,
103, 104
CBEBPIN7-4
CBEBPIN3-0
T/S
PCI bus command and Byte Enables multiplex pins. During the address
phase of a transaction, CBEBPIN7-4 defines the bus command. During the
data phase, CBEBPIN7-4 are used as Byte Enables. The Byte Enables are
valid for the entire data phase and determine which byte lanes carry
meaningful data. CBEBPIN4 applies to byte 4, and CBEBPIN7 applies to
byte 7.
T/S 44, 60, 77, 92 PCI bus command and Byte Enables multiplex pins. During the address
phase of a transaction, CBEBPIN3-0 defines the bus command. During the
data phase, CBEBPIN3-0 are used as Byte Enables. The Byte Enables are
valid for the entire data phase and determine which byte lanes carry
meaningful data. CBEBPIN0 applies to byte 0, and CBEBPIN3 applies to
byte 3.
PCICLK
I
28
PCI Clock: This clock input provides timing for all PCI transactions and is
input to the PCI device. Supports up to a 66MHz PCI clock.
CLKRUNB
I/O
65
Clock Run: This signal is used by the RTL8110SC(L) to request starting (or
speeding up) of the PCICLK clock. CLKRUNB also indicates the clock
status. For the RTL8110SC(L), CLKRUNB is an open drain output as well
as an input. The RTL8110SC(L) requests the central resource to start, speed
up, or maintain the interface clock by the assertion of CLKRUNB. For the
host system, it is an S/T/S signal. The host system (central resource) is
responsible for maintaining CLKRUNB asserted, and for driving it high to
the negated (deasserted) state.
DEVSELB
FRAMEB
S/T/S
S/T/S
68
61
Device Select: As a bus master, the RTL8110SC(L) samples this signal to
insure that a PCI target recognizes the destination address for the data
transfer. As a target, the RTL8110SC(L) asserts this signal low when it
recognizes its target address after FRAMEB is asserted.
Cycle Frame: As a bus master, this pin indicates the beginning and duration
of an access. FRAMEB is asserted low to indicate the start of a bus
transaction. While FRAMEB is asserted, data transfer continues. When
FRAMEB is de-asserted, the transaction is in the final data phase.
As a target, the device monitors this signal before decoding the address to
check if the current transaction is addressed to it.
GNTB
I
29
Grant: This signal is asserted low to indicate to the RTL8110SC(L) that the
central arbiter has granted the ownership of the bus to the RTL8110SC(L).
This input is used when the device is acting as a bus master.
Integrated Gigabit Ethernet Controller (LOM) (MiniPCI)
5
Track ID: JATR-1076-21 Rev. 1.2
REALTEK [ Realtek Semiconductor Corp. ]
