ALC5642-VF
Datasheet
7.4.1. Phase-Locked Loop
A Phase-Locked Loop (PLL) is used to provide a flexible input clock from 2.048MHz to 40MHz. The
source of the PLL can be set to MCLK, BCLK1 or BCLK2 by setting register.
The S/W driver can set up the PLL to output a frequency to match the requirement of system clock.
The PLL transmit formula as below:
FOUT = (MCLK * (N+2)) / ((M+2) * (K+2)) {Typical K=2}
Table 10. Clock Setting Table for 48K (Unit: MHz)
MCLK
13
N
M
7
FVCO
98.222
98.304
98.304
98.304
98.4
K
2
2
2
2
2
2
2
2
2
2
FOUT
24.555
24.576
24.576
24.576
24.6
66
78
94
70
80
81
78
80
78
39
3.6864
2.048
4.096
12
1
0
1
8
15.36
16
11
11
14
14
8
98.068
98.462
98.4
24.517
24.615
24.6
19.2
19.68
24
98.4
24.6
98.4
24.6
Table 11. Clock Setting Table for 44.1K (Unit: MHz)
MCLK
13
N
M
8
FVCO
91
K
2
2
2
2
2
2
2
2
2
2
FOUT
68
72
86
64
66
63
66
64
67
62
22.75
3.6864
2.048
4.096
12
1
90.931
90.112
90.112
90.667
90.764
90.667
90.514
90.528
90.352
22.733
22.528
22.528
22.667
22.691
22.667
22.629
22.632
22.588
0
1
7
15.36
16
9
10
12
13
15
19.2
19.68
24
Multi-Channel Audio Hub/CODEC with embedded Voice
DSP and SounzRealTM Digital Sound Effect
17
Rev. 0.93
REALTEK [ Realtek Semiconductor Corp. ]
