WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port
Table 8: DSPI Instruction Word
Signal
Mnemonic Bit
Description
Read/Write
RW
15
Read/Write Control. RW is asserted to logic ‘1’ for a read
cycle. RW is cleared to logic ‘0’ for write cycle.
Opcode
Address
OP
A
14...10 Instruction opcode.
9...0
MaxArias physical memory address.
The read/write bit (RW) sets the data direction of the subsequent data word(s). On write cycles, the host
continues to drives the DSPI bus with data words. The MaxArias WM72016 uses the rising edge of CLK to
register data presented on D0 and D1. On read cycles, the host drives the DSPI bus with the instruction word,
then tri-states the D0 and D1 signals while receiving data from MaxArias memory.
The opcode (OP) parameter is a 5-bit value that can take on the following values shown in Table 9:
Table 9: DSPI Opcode Values
Mnemonic
NORM
INTEND
-
OPCODE[4:0]
Description
11001
Normal read/write instruction.
Interrupt end instruction.
RESERVED
11101
Others
Two instruction opcodes available in the WM72016 are:
1. NORM – normal opcode for all read/write instructions, and
2. INTEND – DSPI serial port control register opcode.
The address parameter of the DSPI instruction word is a 10-bit value capable of addressing the entire
WM72016 1024-word physical memory. Physical memory addressing is shown in the left-most column in
Table 1:. In the event that memory arbitration is required between the RFID and serial interfaces, the RFID
interface will always have priority. The only exception to this rule is WM72016 interrupt generation, during
which time the serial port has full control over the memory. Care needs to be taken to ensure that reserved
memory required to store critical parameters for the operation of the device are not tampered with.
DSPI Data Streaming
Data may be streamed into the WM72016 (write cycles) or out of WM72016 (read cycles) using a single
instruction word and 2 or more consecutive data words as shown in Figure 13. The example shown in the
figure depicts n+1 data words. The host microcontroller beings the read or write instruction in the same
manner as detailed earlier: the CS signal is asserted, followed by 8 CLK cycles to shift the instruction word
and 8 CLK cycles to shift the data word. From this point forward, each set of 8 CLK cycles is used to read or
write the next WM72016 memory location. While the CS signal remains at a logic one, the WM72016
automatically increments an internal address pointer after every data word cycle has completed. The state of
the AUTOINCR bit in the Control/Status register and the contents of the Working Stored Address have no
impact on DSPI data streaming. Likewise, AUTOINCR and the Working Stored Address register are not
affected by DSPI serial port data streaming. The data streaming cycle is terminated once CS has been cleared
to a logic zero. The DSPI streaming capability removes the requirement for multiple instruction words, greatly
improving bandwidth requirements.
CS
...
CLK
D1
INSTR_WORD
INSTR_WORD
DATA_WORD0
DATA_WORD0
DATA_WORD1
DATA_WORD1
...
...
DATA_WORDn
DATA_WORDn
D0
Figure 13. DSPI Data Streaming
Rev. 1.2
Sept. 2010
Page 14 of 21
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
