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WM72016-NBSD-DS 参数 Datasheet PDF下载

WM72016-NBSD-DS图片预览
型号: WM72016-NBSD-DS
PDF下载: 下载PDF文件 查看货源
内容描述: [Memory Circuit, PDSO8, 3 X3 MM, 0.65 MM PITCH, GREEN, UDFN-8]
分类和应用: 光电二极管内存集成电路
文件页数/大小: 21 页 / 1955 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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WM72016 – Secure F-RAM with Gen-2 RFID and Serial Port  
DSPI write cycles are detailed in Figure 11 below. The host microcontroller drives all 4 DSPI signals for the  
duration of the cycle. The WM72016 uses the rising edge of CLK to shift in the 2 data bits presented on the  
D1 and D0 signals. The host microcontroller shall obey the timing constraints detailed in Table 7:. The host  
microcontroller asserts the 2 data bits prior to the rising edge of CLK. The host microcontroller shifts the  
instruction word with the first set of 8 CLK cycles and shifts the data word on the second set of 8 CLK cycles.  
The write cycle is terminated by clearing the CS signal.  
Figure 11. DSPI Write Cycle Detail  
Table 7: AC Timing - DSPI Interface (2.0V<VDDR<3.6V, -40oC<TA<+85oC)  
Parameter  
Min  
10ns  
10ns  
10ns  
10ns  
10ns  
1.6µs  
tCLK/2  
Max  
Description  
tCSD  
tCSH  
tSU  
tHD  
tDD  
-
Chip select setup to data assertion time.  
Chip select hold time.  
Data setup time.  
-
tCLK/2 - 10ns  
1/tCLK – 10ns  
Data hold time.  
Read data assert time.  
Clock period.  
TBD  
tCLK  
twd  
-
-
Instruction to data word timing.  
DSPI read cycles are detailed in Figure 12. The host microcontroller shall transmit the instruction word in the  
same manner as done for DSPI write cycles. The WM72016 uses the rising edge of CLK to shift in the 2 data  
bits presented on the D1 and D0 signals. Once the instruction word has been completely transmitted and the  
CLK signal has been cleared to a logic zero, the host shall tri-state the D1 and D0 signals allowing the  
WM72016 to drive the data bits for the remainder of the read cycle. The WM72016 shall shift a pair of data  
bits on D1 and D0 on the rising edge of CLK – the host shall use the falling edge of CLK to capture the data  
pair into its shift register. The host shall transmit a total of 8 CLK cycles to receive the entire data word, after  
which it clears the CS to a logic zero to terminate the read cycle.  
Figure 12. DSPI Read Cycle Detail  
The syntax of the instruction word is detailed in Table 8: below.  
Rev. 1.2  
Sept. 2010  
Page 13 of 21