72Mbit Pipelined BSRAM
w/ NoBL Architecture
2Mx36
Preliminary Data Sheet
TAP Registers
Registers are connected between the TDI and TDO pins and allow scanning of data into and out of the SRAM test
circuitry. Only one register can be selected at a time through the Instruction register. Data is serially loaded through the
TDI pin on the rising edge of TCK, and output through the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the Instruction register. This register is loaded when it is placed
between the TDI and TDO pins as shown in the TAP Controller Block Diagram. At power-up, the Instruction register
is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a
reset state as described in the previous section “Performing a TAP Reset”.
When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern
to allow for fault isolation of the board level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The
Bypass register is a single-bit register that can be placed between the TDI and TDO pin, allowing data to shift through
the SRAM with minimal delay. The Bypass register is set low when the Bypass instruction is executed.
Boundary Scan Register
This 70-bit register is connected to all input and output pins on the SRAM. Several no-connect (NC) pins are included
in the Boundary Scan register to reserve pins for higher density devices.
The Boundary Scan register is loaded with the current states on the inputs and outputs of the pad ring when the TAP
controller enters the Capture-DR state, and is then placed between the TDI and TDO pins when the controller enters
the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE-Z instructions can be used to capture the
contents of the pad ring.
The Boundary Scan Order table shows the order in which the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor specific, 32-bit code during the Capture-DR state when the IDCODE command
is loaded in the Instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP
controller is `in the Shift-DR state. The ID register has a vendor code and other information described in the
Identification Register Definitions table.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Copyright 2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 17 of 30
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
