72Mbit Pipelined BSRAM
w/ NoBL Architecture
2Mx36
Preliminary Data Sheet
Output Timing
1
2
3
4
5
6
7
CLK
Command
G#
Read
DS/Wr
tCLZ
tOH
tCO
tCHZ
DQ
Output
-6
-7.5
-10
Symbol
Parameter
Units
Notes
Min
Max
3.5
3.5
-
Min
-
Max
4.2
4.2
-
Min
Max
5.0
5.0
-
tCO
tGV
Data Valid After CLK Rise
G# Low to Output Valid
Data Output Hold
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
1
-
2,3
tOH
1.5
1.5
1.5
-
1.5
1.5
1.5
-
1.5
1.5
1.5
-
tCHZ
tCLZ
tGHZ
tGLZ
Clock to High-Z
3.5
-
3.5
-
3.5
-
1,2,3,4
1,2,3,4
1,2,4
Clock to Low-Z
G# High to Output High-Z
G# Low to Output Low-Z
3.3
-
4.0
-
4.8
-
0
0
0
1,2,4
Notes:
1. AC test conditions assume a signal transition time of 2.0 ns or less, timing reference levels, input pulse levels, and output loading as shown in
the Test Loads circuit diagram.
2. tCHZ, tCLZ, tGHZ, and tGLZ are specified with AC test conditions shown in the Test Loads circuit diagram. Transition is measured + 200mV from
steady-state voltage.
3. At any given voltage and temperature, tGHZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst-case user conditions. The device
is designed to achieve High-Z prior to Low-Z under the same system conditions.
4. This parameter is sampled and not 100% tested.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
Copyright 2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 13 of 30
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
