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SM51209BLDT-7.5 参数 Datasheet PDF下载

SM51209BLDT-7.5图片预览
型号: SM51209BLDT-7.5
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM Module, 64MX72, 5.4ns, CMOS, DIMM-168]
分类和应用: 动态存储器内存集成电路
文件页数/大小: 20 页 / 132 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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168-pin Low Profile SDRAM DIMMs  
32MB, 64MB, 128MB, 256MB, 512MB  
Data Sheet  
Serial Presence Detect (SPD) for SDRAM DIMMs  
256MB  
512MB  
256MB  
512MB  
Byte Description  
** Hex Code **  
0
1
2
3
4
5
6
Number of bytes written into EEPROM  
Total number of SPD bytes  
Memory Type  
Number of Row Addresses  
Number of Column Addresses  
Number of Module Banks  
128  
256  
SDRAM  
12  
10  
2
x64  
x72  
128  
256  
SDRAM  
13  
10  
2
x64  
x72  
0
80  
08  
04  
0C  
0A  
02  
40  
48  
00  
01  
75  
54  
00  
02  
80  
08  
00  
08  
01  
8F  
04  
06  
01  
01  
00  
07  
A0  
60  
00  
00  
14  
14  
14  
2D  
20  
15  
08  
15  
08  
00  
12  
AE  
C0  
80  
08  
04  
0D  
0A  
02  
40  
48  
00  
01  
75  
54  
00  
02  
82  
08  
00  
08  
01  
8F  
04  
06  
01  
01  
00  
07  
A0  
60  
00  
00  
14  
14  
14  
2D  
40  
15  
08  
15  
08  
00  
12  
D1  
E3  
Module Data Width  
x64  
x72  
7
8
Module Data Width (cont'd)  
Voltage Interface Levels  
0
LVTTL  
7.5 ns  
5.4 ns  
LVTTL  
7.5 ns  
5.4 ns  
9
10  
11  
Cycle Time at max CAS Latency  
SDRAM Clock Access Time  
DIMM config (non-parity, parity, ECC)  
--- Non-parity ---  
--- ECC ---  
--- 15.625us / Self ---  
12  
13  
14  
Refresh Rate and Type  
Primary SDRAM Width  
Error Checking Data Width  
7.8 us  
x8  
N/A  
x8  
x8  
N/A  
x8  
x64  
x72  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
Min. CAS-to-CAS Delay (tCCD)  
Burst Lengths Supported  
Number of Banks on SDRAM Device  
CAS Latencies Supported  
CS Latency  
1 clk  
1 clk  
--- 1,2,4,8,Full Pg ---  
4
2,3  
0
4
2,3  
0
Write Latency  
0
0
SDRAM Module Attributes  
SDRAM Device Attributes  
Min. Clock Cycle Time at CL=2  
Clock Access Time at CL=2 (tAC2)  
Min. Clock Cycle Time at CL=1  
Clock Access Time at CL=1 (tAC1)  
Min. Row Precharge Time (tRP)  
Min. Row-to-Row Delay (tRRD)  
Min. RAS-to-CAS Delay (tRCD)  
Min. RAS Pulse Width (tRAS)  
Density of each bank on module  
Cmd/Addr input set-up time  
Cmd/Addr input hold time  
Data input set-up time  
--- Unbuffered ---  
+/-10% Vdd, Precharge All  
10 ns  
6.0 ns  
N/A  
10 ns  
6.0 ns  
N/A  
N/A  
N/A  
20 ns  
20 ns  
20 ns  
45 ns  
128 MB  
20 ns  
20 ns  
20 ns  
45 ns  
256 MB  
1.5 ns  
0.8 ns  
1.5 ns  
0.8 ns  
Data input hold time  
36-61 Superset Information  
-
-
-
-
62  
63  
SPD Rev.  
Checksum for bytes 0-62  
1.2  
x64  
x72  
64-71 JEDEC ID code  
Enhanced Memory Systems  
7F32FFFFFFFFFFFF  
72  
Manufacturing Location  
-
-
xxxx  
xxxx  
xxxx  
rrrr  
xxxx  
xxxx  
xxxx  
rrrr  
73-90 Manufacturer's Part #  
x64  
x72  
SM25608ALDT  
SM25609ALDT  
SM51208BLDT  
SM51209BLDT  
91,92 PCB Rev. Code  
-
93,94 Manufacturing Date  
95-98 Assembly Serial #  
99-125 Manufacturer's Specific Data  
126 Intel specification frequency  
yyww code  
serial number  
open  
yyww  
ssss  
00  
yyww  
ssss  
00  
100MHz  
64  
64  
127 Intel specification CL and clock support  
128-255 Open for Customer Use  
-
-
-
-
AF  
00  
FF  
00  
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921  
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com  
2001 Enhanced Memory Systems. All rights reserved.  
The information contained herein is subject to change without notice.  
Revision 1.1  
Page 17 of 20  
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