168-pin Low Profile SDRAM DIMMs
32MB, 64MB, 128MB, 256MB, 512MB
Data Sheet
AC Operating Conditions (TA = 0°C to 70°C)
Clock and Clock Enable Parameters
Symbol
Parameter
-7.5
Units
Notes
Min
10
Max
tCK2
tCK3
Clock Cycle Time, CL = 2
Clock Cycle Time, CL = 3
-
ns
ns
ns
ns
ns
ns
ns
ns
7.5
2.5
2.5
1.5
0.8
1.5
0.3
-
tCKH2, tCKL2 Clock High & Low Times, CL=2
tCKH3, tCKL3 Clock High & Low Times, CL=3
-
1
1
-
-
tCKES
tCKEH
tCKSP
Clock Enable Set-Up Time
Clock Enable Hold Time
-
CKE Set-Up Time (Power down mode)
Transition Time (Rise and Fall)
-
tT
1.2
Notes:
1. Assumes clock rise and fall times are equal to 1ns. If rise or fall time exceeds 1ns, other AC timing parameters must be compensated by an
additional [(trise+tfall)/2-1] ns.
Common Parameters
Symbol
Parameter
-7.5
Units
Notes
Min
1.5
0.8
20
67
45
20
15
7.5
2
Max
tCS
Command and Address Set-Up Time
Command and Address Hold Time
RAS to CAS Delay Time
-
ns
ns
tCH
-
tRCD
tRC
tRAS
tRP
-
ns
Bank Cycle Time
-
ns
Bank Active Time
100K
ns
Precharge Time
-
-
-
-
ns
tRRD
tCCD
tMRD
Bank to Bank Delay Time (Alt. Bank)
CAS to CAS Delay Time (Same Bank)
Mode Register Set to Active Delay
ns
ns
CLK
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 14 of 20
Revision 1.1
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
