168-pin Low Profile SDRAM DIMMs
32MB, 64MB, 128MB, 256MB, 512MB
Data Sheet
Read and Write Parameters
Symbol
Parameter
-7.5
Units
Notes
Min
-
Max
tAC3
tAC2
tOH3
tOH2
tLZ
Clock Access Time, CL = 3
Clock Access Time, CL = 2
Data Output Hold Time (CL=3)
Data Output Hold Time (CL=2)
Data Output to Low-Z Time
Data Output to High-Z Time (CL=2, 3)
DQM Data Output Disable Time
Data Input Set-Up Time
5.4
ns
ns
1,2
1,2
-
6.0
3.0
3.0
1
-
-
-
7
-
-
-
-
-
-
ns
ns
ns
tHZ2
tDQZ
tDS
3
ns
3
4
2
CLK
ns
1.5
0.8
15
35
0
tDH
Data Input Hold Time
ns
tDPL
tDAL
Data Input to Precharge
ns
Data Input to ACTV/Refresh
Data Write Mask Latency
ns
tDQW
CLK
Notes:
1. Access time is measured at 1.4V (LVTTL) at max clock rate for the CAS latency specified. See AC Test Load.
2. Access time is based on a clock rise time of 1ns. If clock rise time is longer than 1ns, then (trise/2-0.5) ns must be added to the access time.
3. Referenced to the time at which the output achieves an open circuit condition.
4. tDAL is equal to tDPL + tRP.
Refresh Parameters
Symbol
Parameter
-7.5
Units
Notes
Min
Max
64
-
tREF
Refresh Period
Self Refresh Exit Time
-
ms
ns
1,2
3
tSREX
2CLK+tRC
Notes:
1. 4096 cycles (512MB DIMM requires 8192 cycles).
2. Any time that the refresh period has been exceeded, a minimum of two Auto-Refresh (CBR) commands must be given to “wake up” the device.
3. Self-Refresh exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self-Refresh Exit is not
completed until tRC is satisfied once the Self-Refresh Exit command is registered.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2001 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.1
Page 15 of 20
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
