64Mbit – High Speed SDRAM
8Mx8, 4Mx16 HSDRAM
Operating Currents (T
A
= 0°C to 70°C)
Parameter
Operating Current
(One Bank Active)
Standby Current in Power Down
Mode (DRAM Precharged)
Symbol
I
CC1A
I
CC2P
I
CC2PS
Standby Current in Non-Power
Down Mode (DRAM Precharged)
Device Deselected (DRAM
Active)
I
CC2N
I
CC2NS
I
CC3N
I
CC3P
Burst Operating Current
(Both Banks Active)
I
CC4A
I
CC4B
Auto (CBR) Refresh Current
Self Refresh Current
Notes:
1.
2.
3.
4.
5.
Data Sheet
Test Condition
BL = 1, CL = 3, Read or Write,
CKE
V
IH
(min), t
RC
= min., t
CK
= 7.5ns
CKE
V
IL
, t
CK
= 7.5ns,
Input Change Every Two Cycles
CKE
V
IL
, t
CK
= Infinity,
No Input Change
CKE
V
IH
, t
CK
= 7.5ns
CKE
V
IH
, t
CK
= Infinity
CKE
V
IH
, t
CK
= 7.5ns,
Input Change Every Two Cycles
CKE
V
IL
, t
CK
= 7.5ns,
Input Change Every Two Cycles
BL = Full Page, CL = 1, Read or Write,
t
RC
= Infinity, t
CK
= min.
BL = Full Page, CL = 2,3, Read or Write,
t
RC
= Infinity, t
CK
= min.
CL = 3, t
CK
= 7.5ns, t
RC
= t
RC
(min).
CL = 3, t
CK
= 7.5ns, t
RC
= 15.625
µs
CKE
9 1R ,QSXW &KDQJH
Value
120
2.5
2.0
30
10
65
3
70
130
170
30
4
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
1
1,2
1,2
3,4,5
3,4,5
I
CC5F
I
CC5D
I
CC6
The specified value is obtained with the outputs open.
The specified value is obtained when the programmed burst length is executed to completion without intereuption by a subsequent burst read or
burst write cycle.
The specified value is valid when addresses are changed no more than once during t
CK
(min).
The specified value is valid when No Operation commands are registered on every rising clock edge during t
RC
(min).
The specified value is valid when data inputs (DQs) are stable during t
RC
(min).
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
1999 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 8 of 10
Revision 1.1
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
