64Mbit – High Speed SDRAM
8Mx8, 4Mx16 HSDRAM
AC Operating Conditions (T
A
= 0°C to 70°C)
Symbol
Parameter
Min
Clock and Clock Enable Parameters
t
CK3
t
CK2
t
CK1
t
CKH3
, t
CKL3
t
CKH2
, t
CKL2
t
CKH1
, t
CKL1
t
CKES
t
CKEH
t
CKSP
t
T
Clock Cycle Time, CL = 3
Clock Cycle Time, CL = 2
Clock Cycle Time, CL = 1
Clock High & Low Times, CL=3
Clock High & Low Times, CL=2
Clock High & Low Times, CL=1
Clock Enable Set-Up Time
Clock Enable Hold Time
CKE Set-Up Time (Power down mode)
Transition Time (Rise and Fall)
7.5
10
20
2.5
3.5
4.5
1.5
0.8
1.5
-
-
-
-
-
-
-
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-7.5
Max
Units
Data Sheet
Notes
1
1
1
Common Parameters
t
CS
t
CH
t
RCD
t
RC
t
RAS
t
RP
t
RRD
t
CCD
t
MRD
Notes:
1.
Assumes clock rise and fall times are equal to 1ns. If rise or fall time exceeds 1ns, other AC timing parameters must be compensated by an
additional [(t
rise
+t
fall
)/2-1] ns.
Command and Address Set-Up Time
Command and Address Hold Time
RAS to CAS Delay Time
Bank Cycle Time
Bank Active Time
Precharge Time
Bank to Bank Delay Time (Alt. Bank)
CAS to CAS Delay Time (Same Bank)
Mode Register Set to Active Delay
1.5
0.8
15
52.5
37.5
15
15
7.5
2
-
-
-
120K
120K
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
CLK
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
1999 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 6 of 10
Revision 1.1