64Mbit – Enhanced SDRAM
8Mx8, 4Mx16 ESDRAM
Preliminary Datasheet
Extended Mode Register Set Command
This command is an extension of the Mode Register Set command. Please refer to the preceding Mode Register Set
command description for a basic understanding. The Extended Mode Register Set command is used to program DQM
latency and to choose between two output driver impedances.
The Extended Mode Register Set command is activated by issuing a Mode Register Set command with BA1 set high. The
address inputs during this cycle define parameters as shown in the following Extended Mode Register Set diagram.
After an Extended Mode Register Set command, two clocks are required before a new command is issued. If a new Mode
Register Set command is issued, the Extended Mode Register settings revert to their default values.
Extended Mode Register Set (Address Input for Extended Mode Set)
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Operation Mode
Reserved
O/P Z
Rsvd
BA1
1
BA0
0
M11
0
M10
M9
0
M8
0
M7
0
Mode
M1
0
Driver Impedance
Z = 15 ohms (nom.)
Z = 30 ohms (nom.)
0
0
DQM latency = 2
1
0
0
1
0
0
DQM latency = 1 for CL=1
1
Note: This device does not require an EMRS command. The default setting for DQM latency is two, and for driver impedance is 15 Ohms.
DQM Latency
The DQM latency parameter is used to coordinate the data mask function with the CAS latency setting. This allows
simultaneous use of the data mask with a Read command when CAS latency is set to one. DQM latency defaults to two
unless set to one. When CAS latency is set to two or three, this feature is disabled, and DQM latency is always two
regardless of the bits in this register. This feature has no effect on DQM write latency, which always remains at zero
cycles.
Bank Activate Command
The Bank Activate command is issued by holding CAS# and WE# high with CS# and RAS# low at the rising edge of the
clock. BA1 and BA0 specify one of the four banks, and A11-A0 defines the row address to load into its sense amplifiers.
When accessing data that is not already stored in a row cache, a Bank Activate command must be issued before any read
or write is executed.
When a Bank Activate command is given, the row address is decoded and the sense amplifiers hold the selected row data.
However, the row is not loaded into the row cache, and the contents of the cache remain unchanged. The delay between
the Bank Activate command and the first read or write must meet or exceed the RAS to CAS delay time (tRCD). Once a
bank is activated, it must be precharged before another Bank Activate command is applied to the same bank.
The ESDRAM allows the system to issue a Bank Activate command during a burst read cycle. This is because reads occur
from the row cache, not from the DRAM array. Writes, however, require an open page in the DRAM array. So it is not
possible to issue a Bank Activate command during a burst write.
This is a product in sampling or pre-production phase of development. Charac-
teristic data and other specifications are subject to change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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Revision 1.1
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
