Preliminary Datasheet
64Mbit – Enhanced SDRAM
8Mx8, 4Mx16 ESDRAM
Mode Register Set Command
Power On and Initialization
The default power on state of the Mode register is undefined. The following power on and initialization sequence
guarantees the device is preconditioned to each users specific need.
During power on, all V
DD
and V
DDQ
pins must achieve working voltage no later than any of the input signal voltages. The
power on voltage must not exceed V
DD
+ 0.3V on any of the input pins or power supplies. After power on, an initial pause
of 100µs and at least one Deselect command is required followed by a Precharge All Banks command. To avoid data
contention on the DQ bus, it is recommended that the DQM pin(s) are held high during the initial pause period.
Once all four banks are precharged, a minimum of two Auto Refresh (CBR) commands must occur before the Mode
register is programmed. Following the Mode Register Set command, a minimum delay of two clock cycles is required
before the first Bank Activate command. Failure to follow these steps may lead to unpredictable startups.
Programming the Mode Register
For application flexibility, CAS latency, burst length, burst type, and write transfer policy are user defined variables that
must be programmed into the Mode register. This is done with a single Mode Register Set command. Re-executing this
command allows changes to any of these variables, but all four variables must be specified each time.
Before the Mode Register Set command is issued, all four banks must be precharged and CKE must be high at least one
clock cycle. After initial power up, this command must be issued before any Read or Write commands.
The Mode Register Set command is activated when RAS#, CAS#, CS#, and WE# are low at the rising edge of the clock.
The address input data during this cycle defines parameters as shown in the following Mode Register Set diagram. After
this command, a delay of two clock cycles is required before issuing any new command.
Note: Issuing a Mode Register Set command always sets the Extended Mode register to its default settings.
This is a product in sampling or pre-production phase of development. Charac-
teristic data and other specifications are subject to change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
Revision 1.1
Page 7 of 33
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
