64Mbit – Enhanced SDRAM
8Mx8, 4Mx16 ESDRAM
Preliminary Datasheet
Unlike Read commands, which allow reads to continue from the cache while the DRAM row is closed, Write commands
require that the DRAM row remain open, even on a cache (page) hit. When a write is to the row currently in the row
cache, both the cache and the DRAM array are updated to maintain cache coherency. When the write is to another row,
the new row must be activated. This new row is also transferred to the row cache if Write Transfer mode is set in the
Mode register, but not when No Write Transfer mode is set.
If the data mask is activated (DQM high) during a write cycle, the write operation is prohibited immediately with zero
clock latency.
Write Interrupted by a Write
A write burst may be interrupted before completion of the burst by another Write command. When the previous burst is
interrupted, the remaining addresses are ignored, and data is written to the new addresses until the programmed burst
length is satisfied.
Write Interrupted by a Read
A Read command interrupts a Write command on the same clock cycle that the Read command is registered. Only data
present on the DQ pins before the Read command is registered is written to the memory. The data bus must be in the high
impedance state at least one cycle before the interrupting read data appears at the outputs to avoid data contention.
Write Interrupted by a Precharge
A write burst may be terminated by a Precharge command to the same bank. Write data written to the device during the
Precharge command is masked. A write burst to one bank is not terminated by a Precharge command to another bank.
Burst Stop Command
There are several ways to terminate a burst read or burst write prematurely. These methods include using another Read or
Write command to interrupt the existing burst, using a Precharge command to interrupt the burst and close the active
bank, or using the Burst Stop command to terminate the existing burst but leave the bank open for future reads or writes to
the same page of the active bank.
When interrupting a burst with another Read or Write command care must be taken to avoid DQ contention. The Burst
Stop command, however, has fewer restrictions making it the easiest method to use.
The Burst Stop command is issued by holding RAS# and CAS# high, and CS# and WE# low at the rising edge of the
clock. When using this command to stop a read cycle, the DQ pins go to a high impedance state after a delay equal to the
CAS latency set in the Mode register. When the Burst Stop command terminates a write cycle, data on the DQ pins before
the command is registered gets written to the memory.
Auto-Precharge Operation
Before opening a new row in an active bank, the bank must be precharged using either the Precharge command or the
Auto-Precharge function. While decoding the column address the ESDRAM uses the A10/AP pin to allow the active bank
to automatically begin precharge at the earliest possible moment. If A10 is low when a Read or Write command is issued,
normal read or write operation is executed, and the bank remains active. If A10 is high when a Read or Write command is
issued, the Auto-Precharge function is engaged. When a read with auto-precharge is issued, the active bank begins to
precharge on the next clock cycle. Therefore, the precharge is hidden during burst read cycles. The ESDRAM row cache
allows Read commands to execute even after the row is precharged in the DRAM array. Once the precharge starts, the
bank cannot be reactivated until the precharge time (tRP) is satisfied.
This is a product in sampling or pre-production phase of development. Charac-
teristic data and other specifications are subject to change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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