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FM32L274-G 参数 Datasheet PDF下载

FM32L274-G图片预览
型号: FM32L274-G
PDF下载: 下载PDF文件 查看货源
内容描述: 3V集成处理器伴侣与记忆 [3V Integrated Processor Companion with Memory]
分类和应用:
文件页数/大小: 21 页 / 275 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
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FM32L278/L276/L274/L272 - 3V I2C Companion  
DC Operating Conditions, continued (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)  
Symbol Parameter  
Min  
Typ  
Max  
Units Notes  
RIN  
Input Resistance (pulldown)  
A1-A0 for VIN = VIL max  
20  
1
1.175  
KΩ  
MΩ  
V
A1-A0 for VIN = VIH min  
Power Fail Input Reference Voltage  
Power Fail Input (PFI) Hysteresis (Rising)  
VPFI  
1.20  
-
1.225  
100  
VHYS  
mV  
Notes  
1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.  
2. All inputs at VSS or VDD, static. Stop command issued.  
3. VIN or VOUT = VSS to VDD. Does not apply to A0, A1, or /RST pins.  
4. VBAK = 3.0V, VDD < 2.4V, oscillator running, CNT1-2 at VBAK  
.
5. /RST is asserted low when VDD < VTP  
6. The minimum VDD to guarantee the level of /RST remains a valid VOL level.  
7. Full complete operation. Supervisory circuits operate to lower voltages as specified.  
.
8. Includes /RST input detection of external reset condition to trigger driving of /RST signal by FM32L27x.  
9. The VBAK trickle charger automatically regulates the maximum voltage on this pin for capacitor backup applications.  
10. VBAK will source current when trickle charge is enabled (VBC bit=1), VDD > VBAK, and VBAK < VBAK max.  
AC Parameters (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V, CL = 100 pF unless otherwise specified)  
Symbol Parameter  
Min Max Min Max Min Max Units Notes  
fSCL  
tLOW  
tHIGH  
tAA  
SCL Clock Frequency  
0
4.7  
4.0  
100  
0
1.3  
0.6  
400  
0
0.6  
0.4  
1000  
kHz  
µs  
Clock Low Period  
Clock High Period  
SCL Low to SDA Data Out Valid  
µs  
3
0.9  
0.55  
µs  
tBUF  
Bus Free Before New Transmission  
Start Condition Hold Time  
4.7  
4.0  
4.7  
1.3  
0.6  
0.6  
0.5  
0.25  
0.25  
µs  
µs  
µs  
tHD:STA  
tSU:STA  
Start Condition Setup for Repeated  
Start  
tHD:DAT  
tSU:DAT  
tR  
Data In Hold Time  
Data In Setup Time  
Input Rise Time  
0
250  
0
100  
0
100  
ns  
ns  
ns  
ns  
µs  
ns  
ns  
1000  
300  
300  
300  
300  
100  
1
1
tF  
Input Fall Time  
tSU:STO  
Stop Condition Setup Time  
4.0  
0
0.6  
0
0.25  
0
tDH  
tSP  
Data Output Hold (from SCL @ VIL)  
Noise Suppression Time Constant  
on SCL, SDA  
50  
50  
50  
All SCL specifications as well as start and stop conditions apply to both read and write operations.  
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.0V)  
Symbol  
Parameter  
Input/Output Capacitance  
Typ  
-
Max  
8
Units  
pF  
Notes  
1
CIO  
Notes  
1
This parameter is characterized but not tested.  
Data Retention (VDD = 2.7V to 3.6V)  
Symbol  
TDR  
Parameter  
Data Retention  
@ +75°C  
Min  
Units  
Notes  
45  
20  
10  
Years  
Years  
Years  
@ +80°C  
@ +85°C  
Rev. 3.0  
Feb. 2009  
Page 17 of 21  
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