FM32L278/L276/L274/L272 - 3V I2C Companion
three bytes of a write operation to set the internal
address followed by subsequent read operations.
master supplies a Slave Address with the LSB set to
1. This indicates that a read operation is requested.
After receiving the complete Slave Address, the
FM32L27x will begin shifting data out from the
current register address on the next clock. Auto-
increment operates for the special function registers
as with the memory address. A current address read
for the registers look exactly like the memory except
that the device ID is different.
To perform a selective read, the bus master sends out
the slave address with the LSB set to 0. This specifies
a write operation. According to the write protocol,
the bus master then sends the address bytes that are
loaded into the internal address latch. After the
FM32L27x acknowledges the address, the bus master
issues a Start condition. This simultaneously aborts
the write operation and allows the read command to
be issued with the slave address LSB set to a 1. The
operation is now a read from the current address.
Read operations are illustrated below.
The FM32L27x contains two separate address
registers, one for the memory address and the other
for the register address. This allows the contents of
one address register to be modified without affecting
the current address of the other register. For example,
this would allow an interrupted read to the memory
while still providing fast access to a companion
register. A subsequent memory read will then
continue from the memory address where it
previously left off, without requiring the load of a
new memory address. However, a write sequence
always requires an address to be supplied.
Companion Write Operation
All Companion writes operate in a similar manner to
memory writes. The distinction is that a different
device ID is used and only one byte address is needed
instead of two. Figure 16 illustrates a single byte
write to this device.
Companion Read Operation
As with writes, a read operation begins with the
Slave Address. To perform a register read, the bus
No
Acknowledge
Stop
Start
S
Address
By Master
Slave Address
1
A
Data Byte
Data
1
P
By FM32L27x
Acknowledge
Figure 14. Current Address Memory Read
No
Acknowledge
Start
Address
Acknowledge
A
By Master
Stop
S
Slave Address
1
A
Data Byte
Data Byte
1 P
By FM32L27x
Acknowledge
Data
Figure 15. Sequential Memory Read
Rev. 3.0
Feb. 2009
Page 14 of 21
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