欢迎访问ic37.com |
会员登录 免费注册
发布采购

FM32L274-G 参数 Datasheet PDF下载

FM32L274-G图片预览
型号: FM32L274-G
PDF下载: 下载PDF文件 查看货源
内容描述: 3V集成处理器伴侣与记忆 [3V Integrated Processor Companion with Memory]
分类和应用:
文件页数/大小: 21 页 / 275 K
品牌: RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
 浏览型号FM32L274-G的Datasheet PDF文件第9页浏览型号FM32L274-G的Datasheet PDF文件第10页浏览型号FM32L274-G的Datasheet PDF文件第11页浏览型号FM32L274-G的Datasheet PDF文件第12页浏览型号FM32L274-G的Datasheet PDF文件第14页浏览型号FM32L274-G的Datasheet PDF文件第15页浏览型号FM32L274-G的Datasheet PDF文件第16页浏览型号FM32L274-G的Datasheet PDF文件第17页  
FM32L278/L276/L274/L272 - 3V I2C Companion  
user desires to abort a write without altering the  
memory contents, this should be done using a Start  
or Stop condition prior to the 8th data bit. The figures  
below illustrate a single- and multiple-writes to  
memory.  
Stop  
Address & Data  
Start  
S
By Master  
Slave Address  
0
A
Address MSB  
A
Address LSB  
A
Data Byte  
A
P
By FM32L27x  
Acknowledge  
Figure 12. Single Byte Memory Write  
Start  
Stop  
P
Address & Data  
By Master  
S
Slave Address  
0
A
Address MSB  
A
Address LSB  
A
Data Byte  
A
Data Byte  
A
By FM32L27x  
Acknowledge  
Figure 13. Multiple Byte Memory Write  
Each time the bus master acknowledges a byte,  
this indicates that the FM32L27x should read  
out the next sequential byte.  
Memory Read Operation  
There are two types of memory read operations. They  
are current address read and selective address read. In  
a current address read, the FM32L27x uses the  
internal address latch to supply the address. In a  
selective read, the user performs a procedure to first  
set the address to a specific value.  
There are four ways to terminate a read operation.  
Failing to properly terminate the read will most likely  
create a bus contention as the FM32L27x attempts to  
read out additional data onto the bus. The four valid  
methods follow.  
Current Address & Sequential Read  
1. The bus master issues a NACK in the 9th clock  
cycle and a Stop in the 10th clock cycle. This is  
illustrated in the diagrams below and is  
preferred.  
As mentioned above the FM32L27x uses an internal  
latch to supply the address for a read operation. A  
current address read uses the existing value in the  
address latch as a starting place for the read  
operation. The system reads from the address  
immediately following that of the last operation.  
2. The bus master issues a NACK in the 9th clock  
cycle and a Start in the 10th.  
3. The bus master issues a Stop in the 9th clock  
cycle.  
To perform a current address read, the bus master  
supplies a slave address with the LSB set to 1. This  
indicates that a read operation is requested. After  
receiving the complete device address, the  
FM32L27x will begin shifting data out from the  
current address on the next clock. The current address  
is the value held in the internal address latch.  
4. The bus master issues a Start in the 9th clock  
cycle.  
If the internal address reaches the top of memory, it  
will wrap around to 0000h on the next read cycle.  
The figures below show the proper operation for  
current address reads.  
Beginning with the current address, the bus master  
can read any number of bytes. Thus, a sequential read  
is simply a current address read with multiple byte  
transfers. After each byte the internal address counter  
will be incremented.  
Selective (Random) Read  
There is a simple technique that allows a user to  
select a random address location as the starting point  
for a read operation. This involves using the first  
Rev. 3.0  
Feb. 2009  
Page 13 of 21  
 复制成功!