FM31T372/374/376/378-G
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is
controlling the bus is the master. The master is
responsible for generating the clock signal for all
operations. Any device on the bus that is being
controlled is a slave. The FM31T37x is always a
slave device.
Two-wire Interface
The FM31T37x employs an industry standard
two-wire bus that is familiar to many users. This
product is unique since it incorporates two logical
devices in one chip. Each logical device can be
accessed individually. Although monolithic, it
appears to the system software to be two separate
products. One is a memory device. It has a Slave
Address (Slave ID = 1010b) that operates the same
as a stand-alone memory device. The second device
is a real-time clock and processor companion which
have a unique Slave Address (Slave ID = 1101b).
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions:
Start, Stop, Data bit, and Acknowledge. The figure
below illustrates the signal conditions that specify
the four states. Detailed timing diagrams are shown
in the Electrical Specifications section.
SCL
SDA
7
6
0
Stop
Start
Data bits
(Transmitter)
Data bit Acknowledge
(Transmitter) (Receiver)
(Master) (Master)
Figure 9. Data Transfer Protocol
conditions described above, the SDA signal should
not change while SCL is high.
Start Condition
A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a
Start condition. An operation in progress can be
aborted by asserting a Start condition at any time.
Aborting an operation using the Start condition will
ready the FM31T37x for a new operation.
Acknowledge
The Acknowledge (ACK) takes place after the 8th
data bit has been transferred in any transaction.
During this state the transmitter must release the
SDA bus to allow the receiver to drive it. The
receiver drives the SDA signal low to acknowledge
receipt of the byte. If the receiver does not drive
SDA low, the condition is a No-Acknowledge
(NACK) and the operation is aborted.
If the power supply drops below the specified VTP
during operation, any 2-wire transaction in progress
will be aborted and the system must issue a Start
condition prior to performing another operation.
The receiver might NACK for two distinct reasons.
First is that a byte transfer fails. In this case, the
NACK ends the current operation so that the part can
be addressed again. This allows the last byte to be
recovered in the event of a communication error.
Stop Condition
A Stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations must end with a Stop condition.
If an operation is pending when a stop is asserted,
the operation will be aborted. The master must have
control of SDA (not a memory read) in order to
assert a Stop condition.
Second and most common, the receiver does not
send an ACK to deliberately terminate an operation.
For example, during a read operation, the FM31T37x
will continue to place data onto the bus as long as the
receiver sends ACKs (and clocks). When a read
operation is complete and no more data is needed,
the receiver must NACK the last byte. If the receiver
ACKs the last byte, this will cause the FM31T37x to
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
Rev. 1.1
Apr. 2011
Page 16 of 26
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
